NXP Semiconductors /LPC11Exx /SSP0 /CR1

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Interpret as CR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DURING_NORMAL_OPERAT)LBM 0 (DISABLED)SSE 0 (MASTER)MS 0 (SOD)SOD 0RESERVED

LBM=DURING_NORMAL_OPERAT, SSE=DISABLED, MS=MASTER

Description

Control Register 1. Selects master/slave and other modes.

Fields

LBM

Loop Back Mode.

0 (DURING_NORMAL_OPERAT): During normal operation.

1 (SERIAL_INPUT_IS_TAKE): Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).

SSE

SPI Enable.

0 (DISABLED): The SPI controller is disabled.

1 (ENABLED): The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit.

MS

Master/Slave Mode.This bit can only be written when the SSE bit is 0.

0 (MASTER): The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.

1 (SLAVE): The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.

SOD

Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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